1. Field of the Invention
This invention relates to methods and systems to establish a design methodology for operational amplifiers to be used in the design of amplifiers having low total harmonic distortion (THD). In particular this invention relates to methods and systems that will optimize the components such as transistors and compensation capacitors of operational amplifiers to minimize total harmonic distortion for inverting or non-inverting amplifiers designed using these methods and systems.
2. Description of Related Art
Methods and systems for synthesizing logic circuits are known in the art. For instance, U.S. Pat. No. 5,402,357 (Schaefer et al.) discloses a system and method for synthesizing logic circuits with timing constraints. In a computer aided design system, a net list specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The automatic circuit layout synthesis process begins by assigning an initial capacitance value to each node. Next, a routing difficulty value is computed; this value comprises a sum of routing difficulty values associated with each of the nodes in the integrated circuit. Capacitance values for the integrated circuit are then adjusted to reduce the computed routing difficulty. Finally, the net list and adjusted capacitance values are passed to a silicon compiler for automatic placement and routing of a circuit having capacitance values not exceeding the adjusted capacitance values.
Additionally, methods for simulating logic circuits are known in the art. An example of a logic simulation method is shown in U.S. Pat. No. 4,922,445 (Mizoue et al.). The logic circuit simulation method allow the simulating of a logic circuit that includes a plurality of logic blocks. After having simulated the whole simulation object logic circuit, the signal variation information of an arbitrary logic block is taken out from the simulation result. The simulation result that is taken out is to other logic blocks and a renewed simulation is executed for every logic block.
Computer aided design techniques have been developed for analog circuitry as is shown in U.S. Pat. No. 5,046,016 (Krill et al.). Krill et al. describes a method for the computer aided design for TE01 mode circular waveguides. The method will create designs for circular overmoded waveguide systems having optimal operating characteristics. The CAD method receives selected input waveguide operational, material, and structural parameters and computes the resulting waveguide operational characteristics, induding power losses for a given waveguide system configuration, including both straight and bent sections. Optimal designs for lined dielectric and sheathed-helix types of circular waveguide and waveguide bends have resulted for both S- and X-band operation.
Methods and systems for analysis and evaluation of semiconductor circuit performance characteristics are well known in the art and illustrated by U.S. Pat. No. 5,694,052 (Sawai et al.). A characteristic of a MOS transistor is represented using an equivalent model. The equivalent model shows a connection configuration made up of an electric current source that supplies an electric current and a resistor element that is connected in parallel with the electric current source. The electric current is given by the equation of i=Gm * (VGS-VT) for VGS&gt;=VT where Gm is a coefficient, VGS is a gate-to-source input voltage of said MOS transistor, and VT is a given threshold voltage. A plurality of operating zones of the MOS transistor are defined according to the drain, source, and gate terminal voltages of the MOS transistor and are assigned respective values of the coefficient Gm and respective values of the resistor element's resistance. By such a representation, the circuit equation of a semiconductor circuit that is analyzed can be represented in the form of a linear time-invariant equation. Semiconductor circuit performance characteristics can be analyzed and evaluated at high accuracy and high speed.
U.S. Pat. No. 5,714,906 (Motamed et al.) discloses a low voltage constant transconductance input stage. The low voltage, constant transconductance input stage is achieved with relatively simple design methodology. The approach uses current-mode techniques and is based upon the processing of signal currents, rather than handling the bias currents of input stages. Such an approach becomes universal and independent of the input stage transistor types, whether FET or bipolar transistors. Further, the arrangement considerably simplifies the design procedure of low voltage operational amplifiers. MOS and bipolar operational amplifier input stages are described wherein almost constant gm is achieved which is independent of the common mode input voltage ranging from rail-to-rail.
U.S. Pat. No. 4,716,381 (Campbell) describes an operational amplifier suitable for inclusion in an integrated circuit device operating as a transceiver at a coaxial media interface to a network meeting IEEE 802.3 standards. To be included in an integrated circuit package, the operational amplifier must have low-power consumption and yet generate up to 80 ma of current onto the network. A design method achieves this goal producing an operational amplifier having three independently positioned, isolated, poles. A current generator and level shifter is employed with the operational amplifier that generates a current precisely proportional to a "collision" reference voltage. The current is compensated for changes in temperature and for variations in transistor gain (hFE). A very wide band level shifter matches the current generated to the requirements of the operational amplifier so that 10% to 90% changes in current generated by the op amp can occur in 1/2 to 3/4 of a nanosecond, yet the level shifter does not consume much power. The current generator provides a single point of circuit element control for compensating for hFE variation in three transistors used within the current generator. The level shifter employs current-steering to produce the switched current that is exceptionally fast and low in asymmetry. The process used in integrated circuit manufacture permits control of the elements within the operational amplifier so that parameters can be held within 2% of the tolerances specified in the IEEE 802.3 standards without need of field "trimming".
U.S. Pat. No. 5,376,896 (Graefe et al.) discloses a circuit to reduce the level of noise and to reduce distortion of an input audio signal. The input audio signal is equally divided between a pair of Voltage Controlled Amplifiers (VCA). Each VCA receives an equal portion of the audio signal's current and has its gain controlled by a common control voltage. The outputs of the VCA's are summed together and are applied to an inverting input terminal of an operational amplifier. The gain of the VCA's is set at 6 dB and the gain of the op-amp is set at -6 dB. Since the operational amplifier sums the audio signals at 6 dB and sums noise and broadband signals at 3 dB, the signal to noise ratio in the output signal is increased and the noise level, the total harmonic distortion, the intermodulation distortion, and the DC feed through are all reduced in comparison to the input signal.